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#include <stm32f10x.h>

#include <stm32f10x/rcc.h>

#include <stm32f10x/usart.h>

#include <fcntl.h>

#include <errno.h>

#include <stdlib.h>

#include <string.h>

//! Uptime counter

static __IO uint32_t __UptimeCounter = 0;

caddr_t _sbrk_getHeapStartAddress();

caddr_t _sbrk( int Size ) {

// - Current heap end pointer

static caddr_t hHeapEnd;

// - Previous heap end pointer

caddr_t hPrevHeapEnd;

// - Init heap pointer

if ( hHeapEnd == 0 ) hHeapEnd = _sbrk_getHeapStartAddress();

// - Get current stack pointer

caddr_t hStackTop = (caddr_t)__get_MSP();

// - Store current heap pointer

hPrevHeapEnd = hHeapEnd;

// - Check is heap overlaps stack

if( hHeapEnd + Size > hStackTop ) {

errno = ENOMEM;

return (caddr_t)-1;

}

// - Add heap size

hHeapEnd += Size;

// - Return result

return hPrevHeapEnd;

}

int usleep( useconds_t __useconds ){

volatile uint32_t nCount;

RCC_ClocksTypeDef RCC_Clocks;

RCC_GetClocksFreq (&RCC_Clocks);

nCount = ( RCC_Clocks.HCLK_Frequency / 10000000 ) * __useconds;

for( ; nCount !=0 ; nCount-- );

return 0;

}

unsigned int sleep( unsigned int __seconds ){

usleep( __seconds * 1000 * 1000 );

return 0;

}

int _close( int __fd ){

return 0;

}

ssize_t _write( int __fd, const void * __buf, size_t __n ){

uint8_t * Buffer = (uint8_t*)__buf;

switch( __fd ){

// --- USART 1

case 1:{

for( size_t i = 0; i < __n; i++ ){

// - Wait until TX ready

while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET);

// - Send

USART_SendData( USART1, Buffer[ i ] );

}

}; break;

// --- USART 2

case 2:{

for( size_t i = 0; i < __n; i++ ){

// - Wait until TX ready

while(USART_GetFlagStatus(USART2, USART_FLAG_TXE) == RESET);

// - Send

USART_SendData( USART2, Buffer[ i ] );

}

}; break;

// --- USART 3

case 3:{

for( size_t i = 0; i < __n; i++ ){

// - Wait until TX ready

while(USART_GetFlagStatus(USART3, USART_FLAG_TXE) == RESET);

// - Send

USART_SendData( USART3, Buffer[ i ] );

}

}; break;

}

return 0;

}

int _open( const char * __file, mode_t mode ){

if( !strcmp( __file, "/dev/usart1" ) ) return 1;

else if( !strcmp( __file, "/dev/usart2" ) ) return 2;

else if( !strcmp( __file, "/dev/usart3" ) ) return 3;

else return 0;

}

ssize_t _read( int __fd, void * __buf, size_t __nbytes ){

size_t i;

size_t BytesRead = 0;

switch( __fd ){

case 1: {

for( i = 0; i < __nbytes; i++ ){

while (USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET);

char c = (char)(USART_ReceiveData(USART1) & (uint16_t) 0x01FF);

*((char*)__buf) = c;

__buf++; BytesRead++;

}

}; break;

case 2: {

for( i = 0; i < __nbytes; i++ ){

while (USART_GetFlagStatus(USART2, USART_FLAG_RXNE) == RESET);

char c = (char)(USART_ReceiveData(USART2) & (uint16_t) 0x01FF);

*((char*)__buf) = c;

__buf++; BytesRead++;

}

}; break;

case 3: {

for( i = 0; i < __nbytes; i++ ){

while (USART_GetFlagStatus(USART3, USART_FLAG_RXNE) == RESET);

char c = (char)(USART_ReceiveData(USART3) & (uint16_t) 0x01FF);

*((char*)__buf) = c;

__buf++; BytesRead++;

}

}; break;

default:

errno = EBADF;

return -1;

}

return BytesRead;

}

void _exit(int x ) {

while(1);

}

pid_t _getpid( ){

return 1;

}

int _kill( int x ){

return 0;

}

int _fstat(int file, struct stat *st){

st->st_mode = S_IFCHR;

return 0;

}

int _isatty(int file)

{

switch (file)

{

case 1:

case 2:

case 3:

return 1;

default:

//errno = ENOTTY;

errno = EBADF;

return 0;

}

int _lseek(int file, int ptr, int dir){

return 0;

}

uint32_t uptime_ms(){

return __UptimeCounter;

}

void SysTick_Handler(void){

__UptimeCounter++;

}

.syntax unified

.cpu cortex-m3

.fpu softvfp

.thumb

.section .text._sbrk_getHeapStartAddress

.weak _sbrk_getHeapStartAddress

.type _sbrk_getHeapStartAddress, %function

_sbrk_getHeapStartAddress:

ldr r0, = __HeapStart

bx lr

-nostartfiles -mcpu=cortex-m3 -mthumb -TSTM32F103C8T6.ld

-Wl,-Map=~Build/$(ConfigurationName)/$(ProjectName).map -Wl,-gc-sections

arm-none-eabi-size ~Build/$(ConfigurationName)/$(ProjectName).elf

arm-none-eabi-objcopy -Obinary ~Build/$(ConfigurationName)/$(ProjectName).elf ~Build/$(ConfigurationName)/$(ProjectName).bin

arm-none-eabi-objcopy -Oihex ~Build/$(ConfigurationName)/$(ProjectName).elf ~Build/$(ConfigurationName)/$(ProjectName).hex

/* Linker script to configure memory regions. */

MEMORY {

FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 0x20000 /* 128k */

RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x5000 /* 20k */

}

/* Library configurations */

GROUP(libgcc.a libc.a libm.a libSTM32F10X_MD.a)

/* Linker script to place sections and symbol values. Should be used together

* with other linker script that defines memory regions FLASH and RAM.

* It references following symbols, which must be defined in code:

* Reset_Handler : Entry of reset handler

* It defines following symbols, which code can use without definition:

* __exidx_start

* __exidx_end

* __etext

* __data_start__

* __preinit_array_start

* __preinit_array_end

* __init_array_start

* __init_array_end

* __fini_array_start

* __fini_array_end

* __data_end__

* __bss_start__

* __bss_end__

* __end__

* __HeapLimit

* __StackLimit

* __StackTop

* __stack

ENTRY(Reset_Handler)

SECTIONS {

.text : {

KEEP(*(.isr_vector))

*(.text)

*(.text.*)

KEEP(*(.init))

KEEP(*(.fini))

/* .ctors */

*crtbegin.o(.ctors)

*crtbegin?.o(.ctors)

*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

*(SORT(.ctors.*))

*(.ctors)

/* .dtors */

*crtbegin.o(.dtors)

*crtbegin?.o(.dtors)

*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

*(SORT(.dtors.*))

*(.dtors)

*(.rodata*)

KEEP(*(.eh_frame*))

} > FLASH

.ARM.extab : {

*(.ARM.extab* .gnu.linkonce.armextab.*)

} > FLASH

__exidx_start = .;

.ARM.exidx : {

*(.ARM.exidx* .gnu.linkonce.armexidx.*)

} > FLASH

__exidx_end = .;

_sidata = .;

.data : AT ( _sidata ) {

_sdata = .;

*(vtable)

*(.data*)

. = ALIGN(4);

/* preinit data */

PROVIDE (__preinit_array_start = .);

*(.preinit_array)

PROVIDE (__preinit_array_end = .);

. = ALIGN(4);

/* init data */

PROVIDE (__init_array_start = .);

*(SORT(.init_array.*))

*(.init_array)

PROVIDE (__init_array_end = .);

. = ALIGN(4);

/* finit data */

PROVIDE (__fini_array_start = .);

*(SORT(.fini_array.*))

*(.fini_array)

PROVIDE (__fini_array_end = .);

. = ALIGN(4);

/* All data end */

_edata = .;

} > RAM

.bss : {

_sbss = .;

*(.bss*)

*(COMMON)

_ebss = .;

} > RAM

.heap : {

__HeapStart = .;

*(.heap*)

__HeapLimit = .;

} > RAM

/* .stack_dummy section doesn't contains any symbols. It is only

* used for linker to calculate size of stack sections, and assign

* values to stack symbols later */

.stack : {

*(.stack)

} > RAM

/* Set stack top to end of RAM, and stack limit move down by

* size of stack_dummy section */

__StackTop = ORIGIN(RAM) + LENGTH(RAM);

__StackLimit = __StackTop - SIZEOF(.stack);

_estack = __StackTop;

/* Check if data + heap + stack exceeds RAM limit */

ASSERT(__StackLimit >= __HeapLimit, "RAM overflowed with stack")

}

/**

******************************************************************************

* @file startup_stm32f10x_md.s

* @author MCD Application Team

* @version V3.5.0

* @date 11-March-2011

* @brief STM32F10x Medium Density Devices vector table for RIDE7 toolchain.

* This module performs:

* - Set the initial SP

* - Set the initial PC == Reset_Handler,

* - Set the vector table entries with the exceptions ISR address

* - Configure the clock system

* - Branches to main in the C library (which eventually

* calls main()).

* After Reset the Cortex-M3 processor is in Thread mode,

* priority is Privileged, and the Stack is set to Main.

******************************************************************************

* @attention

* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

******************************************************************************

.syntax unified

.cpu cortex-m3

.fpu softvfp

.thumb

.global g_pfnVectors

.global Default_Handler

/* start address for the initialization values of the .data section.

defined in linker script */

.word _sidata

/* start address for the .data section. defined in linker script */

.word _sdata

/* end address for the .data section. defined in linker script */

.word _edata

/* start address for the .bss section. defined in linker script */

.word _sbss

/* end address for the .bss section. defined in linker script */

.word _ebss

.equ BootRAM, 0xF108F85F

/**

* @brief This is the code that gets called when the processor first

* starts execution following a reset event. Only the absolutely

* necessary set is performed, after which the application

* supplied main() routine is called.

* @param None

* @retval : None

.section .text.Reset_Handler

.weak Reset_Handler

.type Reset_Handler, %function

Reset_Handler:

/* Copy the data segment initializers from flash to SRAM */

movs r1, #0

b LoopCopyDataInit

CopyDataInit:

ldr r3, =_sidata

ldr r3, [r3, r1]

str r3, [r0, r1]

adds r1, r1, #4

LoopCopyDataInit:

ldr r0, =_sdata

ldr r3, =_edata

adds r2, r0, r1

cmp r2, r3

bcc CopyDataInit

ldr r2, =_sbss

b LoopFillZerobss

/* Zero fill the bss segment. */

FillZerobss:

movs r3, #0

str r3, [r2], #4

LoopFillZerobss:

ldr r3, = _ebss

cmp r2, r3

bcc FillZerobss

/* Call the clock system intitialization function.*/

bl SystemInit

/* Call the application's entry point.*/

bl main

bx lr

.size Reset_Handler, .-Reset_Handler

/**

* @brief This is the code that gets called when the processor receives an

* unexpected interrupt. This simply enters an infinite loop, preserving

* the system state for examination by a debugger.

* @param None

* @retval None

.section .text.Default_Handler,"ax",%progbits

Default_Handler:

Infinite_Loop:

b Infinite_Loop

.size Default_Handler, .-Default_Handler

/******************************************************************************

* The minimal vector table for a Cortex M3. Note that the proper constructs

* must be placed on this to ensure that it ends up at physical address

* 0x0000.0000.

******************************************************************************/

.section .isr_vector,"a",%progbits

.type g_pfnVectors, %object

.size g_pfnVectors, .-g_pfnVectors

g_pfnVectors:

.word _estack

.word Reset_Handler

.word NMI_Handler

.word HardFault_Handler

.word MemManage_Handler

.word BusFault_Handler

.word UsageFault_Handler

.word 0

.word SVC_Handler

.word DebugMon_Handler

.word 0

.word PendSV_Handler

.word SysTick_Handler

.word WWDG_IRQHandler

.word PVD_IRQHandler

.word TAMPER_IRQHandler

.word RTC_IRQHandler

.word FLASH_IRQHandler

.word RCC_IRQHandler

.word EXTI0_IRQHandler

.word EXTI1_IRQHandler

.word EXTI2_IRQHandler

.word EXTI3_IRQHandler

.word EXTI4_IRQHandler

.word DMA1_Channel1_IRQHandler

.word DMA1_Channel2_IRQHandler

.word DMA1_Channel3_IRQHandler

.word DMA1_Channel4_IRQHandler

.word DMA1_Channel5_IRQHandler

.word DMA1_Channel6_IRQHandler

.word DMA1_Channel7_IRQHandler

.word ADC1_2_IRQHandler

.word USB_HP_CAN1_TX_IRQHandler

.word USB_LP_CAN1_RX0_IRQHandler

.word CAN1_RX1_IRQHandler

.word CAN1_SCE_IRQHandler

.word EXTI9_5_IRQHandler

.word TIM1_BRK_IRQHandler

.word TIM1_UP_IRQHandler

.word TIM1_TRG_COM_IRQHandler

.word TIM1_CC_IRQHandler

.word TIM2_IRQHandler

.word TIM3_IRQHandler

.word TIM4_IRQHandler

.word I2C1_EV_IRQHandler

.word I2C1_ER_IRQHandler

.word I2C2_EV_IRQHandler

.word I2C2_ER_IRQHandler

.word SPI1_IRQHandler

.word SPI2_IRQHandler

.word USART1_IRQHandler

.word USART2_IRQHandler

.word USART3_IRQHandler

.word EXTI15_10_IRQHandler

.word RTCAlarm_IRQHandler

.word USBWakeUp_IRQHandler

.word 0

.word BootRAM /* @0x108. This is for boot in RAM mode for

STM32F10x Medium Density devices. */

/*******************************************************************************

* Provide weak aliases for each Exception handler to the Default_Handler.

* As they are weak aliases, any function with the same name will override

* this definition.

*******************************************************************************/

.weak NMI_Handler

.thumb_set NMI_Handler,Default_Handler

.weak HardFault_Handler

.thumb_set HardFault_Handler,Default_Handler

.weak MemManage_Handler

.thumb_set MemManage_Handler,Default_Handler

.weak BusFault_Handler

.thumb_set BusFault_Handler,Default_Handler

.weak UsageFault_Handler

.thumb_set UsageFault_Handler,Default_Handler

.weak SVC_Handler

.thumb_set SVC_Handler,Default_Handler

.weak DebugMon_Handler

.thumb_set DebugMon_Handler,Default_Handler

.weak PendSV_Handler

.thumb_set PendSV_Handler,Default_Handler

.weak SysTick_Handler

.thumb_set SysTick_Handler,Default_Handler

.weak WWDG_IRQHandler

.thumb_set WWDG_IRQHandler,Default_Handler

.weak PVD_IRQHandler

.thumb_set PVD_IRQHandler,Default_Handler

.weak TAMPER_IRQHandler

.thumb_set TAMPER_IRQHandler,Default_Handler

.weak RTC_IRQHandler

.thumb_set RTC_IRQHandler,Default_Handler

.weak FLASH_IRQHandler

.thumb_set FLASH_IRQHandler,Default_Handler

.weak RCC_IRQHandler

.thumb_set RCC_IRQHandler,Default_Handler

.weak EXTI0_IRQHandler

.thumb_set EXTI0_IRQHandler,Default_Handler

.weak EXTI1_IRQHandler

.thumb_set EXTI1_IRQHandler,Default_Handler

.weak EXTI2_IRQHandler

.thumb_set EXTI2_IRQHandler,Default_Handler

.weak EXTI3_IRQHandler

.thumb_set EXTI3_IRQHandler,Default_Handler

.weak EXTI4_IRQHandler

.thumb_set EXTI4_IRQHandler,Default_Handler

.weak DMA1_Channel1_IRQHandler

.thumb_set DMA1_Channel1_IRQHandler,Default_Handler

.weak DMA1_Channel2_IRQHandler

.thumb_set DMA1_Channel2_IRQHandler,Default_Handler

.weak DMA1_Channel3_IRQHandler

.thumb_set DMA1_Channel3_IRQHandler,Default_Handler

.weak DMA1_Channel4_IRQHandler

.thumb_set DMA1_Channel4_IRQHandler,Default_Handler

.weak DMA1_Channel5_IRQHandler

.thumb_set DMA1_Channel5_IRQHandler,Default_Handler

.weak DMA1_Channel6_IRQHandler

.thumb_set DMA1_Channel6_IRQHandler,Default_Handler

.weak DMA1_Channel7_IRQHandler

.thumb_set DMA1_Channel7_IRQHandler,Default_Handler

.weak ADC1_2_IRQHandler

.thumb_set ADC1_2_IRQHandler,Default_Handler

.weak USB_HP_CAN1_TX_IRQHandler

.thumb_set USB_HP_CAN1_TX_IRQHandler,Default_Handler

.weak USB_LP_CAN1_RX0_IRQHandler

.thumb_set USB_LP_CAN1_RX0_IRQHandler,Default_Handler

.weak CAN1_RX1_IRQHandler

.thumb_set CAN1_RX1_IRQHandler,Default_Handler

.weak CAN1_SCE_IRQHandler

.thumb_set CAN1_SCE_IRQHandler,Default_Handler

.weak EXTI9_5_IRQHandler

.thumb_set EXTI9_5_IRQHandler,Default_Handler

.weak TIM1_BRK_IRQHandler

.thumb_set TIM1_BRK_IRQHandler,Default_Handler

.weak TIM1_UP_IRQHandler

.thumb_set TIM1_UP_IRQHandler,Default_Handler

.weak TIM1_TRG_COM_IRQHandler

.thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler

.weak TIM1_CC_IRQHandler

.thumb_set TIM1_CC_IRQHandler,Default_Handler

.weak TIM2_IRQHandler

.thumb_set TIM2_IRQHandler,Default_Handler

.weak TIM3_IRQHandler

.thumb_set TIM3_IRQHandler,Default_Handler

.weak TIM4_IRQHandler

.thumb_set TIM4_IRQHandler,Default_Handler

.weak I2C1_EV_IRQHandler

.thumb_set I2C1_EV_IRQHandler,Default_Handler

.weak I2C1_ER_IRQHandler

.thumb_set I2C1_ER_IRQHandler,Default_Handler

.weak I2C2_EV_IRQHandler

.thumb_set I2C2_EV_IRQHandler,Default_Handler

.weak I2C2_ER_IRQHandler

.thumb_set I2C2_ER_IRQHandler,Default_Handler

.weak SPI1_IRQHandler

.thumb_set SPI1_IRQHandler,Default_Handler

.weak SPI2_IRQHandler

.thumb_set SPI2_IRQHandler,Default_Handler

.weak USART1_IRQHandler

.thumb_set USART1_IRQHandler,Default_Handler

.weak USART2_IRQHandler

.thumb_set USART2_IRQHandler,Default_Handler

.weak USART3_IRQHandler

.thumb_set USART3_IRQHandler,Default_Handler

.weak EXTI15_10_IRQHandler

.thumb_set EXTI15_10_IRQHandler,Default_Handler

.weak RTCAlarm_IRQHandler

.thumb_set RTCAlarm_IRQHandler,Default_Handler

.weak USBWakeUp_IRQHandler

.thumb_set USBWakeUp_IRQHandler,Default_Handler